MONDAY, June 10, 2002 09:00 AM - 12:00 PM | Room: 293    HANDS ON TUTORIAL    Developing Bus-Functional Models for Embedded ATM Switch Verification    Organizers: SynaptiCAD Inc. and Synopsys, Inc.      SynaptiCAD and Synopsys will offer a hands-on tutorial where the attendees will construct an OpenVera test bench to verify an embedded ATM network switch using SynaptiCAD's graphical code generator TestBencher Pro and Synopsys's VERA test bench tool. Attendees will learn state of the art verification techniques, including modeling of data flow, random generation and ordering data cells and authentication of data that flows out of the device. The constructed test bench will also manage synchronization issues, avoid race conditions, and use algorithms and data structures that have traditionally only been needed for software verification. While the example used in this tutorial is an ATM switch, these techniques are beneficial for testing virtually all complex designs, particularly designs where hardware is replacing software functionality. Attendees will use SynaptiCAD's TestBencher Pro to graphically describe transmit and receive transactions. TestBencher will generate OpenVera code directly from the graphical descriptions. Attendees will get a brief overview of OpenVera code. Next the attendees will compile the OpenVera test bench using the Synopsys VERA tool. Finally users will link the VERA run time object to the Verilog model of the ATM switch, simulate the design using Synopsys's VCS Verilog simulator, and analyze the simulation results.